1. Field of the Invention
Embodiments of the invention generally relate to planarization of semiconductor devices and to methods and compositions for material removal using polishing techniques.
2. Description of the Related Art
The semiconductor industry's focus to push semiconductor performance ever faster has recently shifted from front-end device performance to back-end interconnects. The multilevel interconnects that lie at the heart of semiconductor technology require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects and reliable production of 0.13 micron and smaller features are important to the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) and to the continued effort to increase circuit density and quality of individual substrates and die.
Planarization is useful in damascene interconnect processes to remove excess deposited materials and to provide a planar surface for subsequent levels of metallization and processing. Planarization may also be used in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated materials. Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes two modes to planarize substrates. One is a chemical composition, typically a slurry, a polishing composition, or other fluid medium, for removal of materials from substrates, and the other is mechanical force, applying onto the substrate through a polishing pad, such as a conventional polishing pad or a fixed abrasive polishing pad.
As semiconductor device geometries shrink to 0.13 micron or below and the speed of the semiconductor devices decreases, and cross talk between wires and heat delay increases (RC delay). In order to minimize RC delay and to further improve the integration density of semiconductor devices on integrated circuits, the semiconductor industry is using conductive materials having low resistivity (1.7 μΩ-cm for copper compared to 3.1 μΩ-cm for aluminum) for conductors in feature definitions formed in insulating materials having low-k dielectric constants. Low-k is defined herein as having a value of dielectric constant, k, less than about 4.0, which is the k value for traditional SiO2. For example, the dielectric constant for fluorinated silicate glass (FSG) is about 3.6 and that for carbon doped silicon oxide materials is less than about 3.
There are primarily two types of dielectric materials competing at the 0.13 micron or below technology node; carbon doped silicon oxides and spin-on-dielectric materials. Both of these materials create challenges for processing interconnects. Two challenges arise when using low-k dielectric materials: the mechanical hardness of low-k dielectric materials and adhesion at the interface of the low-k material and the adjacent materials. Furthermore, there is a need for a protective layer formed on top of low-k materials to prevent exposure of the low-k material to moisture and to provide good adhesion to the underlying low-k materials. Such undesirable structural and adhesion failures cause damage or defects as a result of aggressive processing and require the shear force or frictional force in a CMP process to be small. Shear force or frictional force is approximately proportional to down load force. Therefore, the requirements further imply that down load force, typically measured in pounds, and polishing pressure, which represents the amount of the down load force divided by the polishing area and typically measured in pounds per square inch (psi), during processing has to be small. Integration approaches for low-k materials must comprehend these basic integration changes, and so an emphasis on characterization techniques for mechanical properties, chemical interactions and dielectric stability becomes important.
Beyond 0.13 micron low-k technology, integration issues are even more difficult. It is believed that future k values will have to be 2.2 or less. One of the pathways to achieve lower k values is to introduce pores into silicon oxide based materials to form porous polymers. The introduction of porosity can result in substantially reduced mechanical integrity of the low-k materials and affect processing performance.
In addition, copper diffuses into surrounding materials, such as the low k dielectric materials. Therefore, barrier materials are deposited in feature definitions formed in the low-k dielectric materials prior to copper deposition to reduce or minimize copper diffusion into the surrounding materials.
Typically, vertical and horizontal interconnects are formed by a damascene or dual damascene process. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, e.g., vias, and horizontal interconnects, e.g., lines. Conductive materials, such as copper-containing materials, and other materials, such as barrier materials used to prevent diffusion of copper-containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper-containing material and any excess barrier material external to the etched pattern, such as on the field of the substrate, are then removed.
After material deposition by the damascene or dual damascene method, the uppermost substrate surface may become non-planar and require planarization. Conventionally, in polishing substrates having features, such as a dual damascene feature formed by the deposition of a barrier layer in an aperture and a conductive layer, such as copper, disposed on the barrier layer, the conductive layer is polished to the barrier layer, and then the barrier layer is polished to the underlying dielectric layer to form the feature. In most conventional applications, erosion and dishing are typically encountered. As used throughout this disclosure, the term “erosion” denotes a difference in height between the dielectric materials in the open field and the dielectric materials within the dense array. The term “dishing” denotes a difference in height between the highest point of the dielectric materials and the center of the copper features.
Erosion of the low-k materials typically occurs within the dense array and is believed to be attributed in part to an increase in pressure due to the presence of recesses and, hence, less copper, generating a pressure differential between the dense array and the open field. Consequently, the removal rate within the dense array is greater than the removal rate in the open field. Additionally, increasing the polishing pressure and increasing the polishing time to ensure copper layer removal may result in overpolishing the barrier layer and formation of topographical defects, such as concavities or depressions, referred to as dishing. Dishing further results in a non-planar surface that impairs the ability to print high-resolution lines during subsequent photolithographic steps and detrimentally affects subsequent surface topography of the substrate and device formation. Dishing also detrimentally affects the performance of devices by lowering the conductance and increasing the resistance of the devices, contrary to the benefit of using higher conductive materials, such as copper.
However, polishing substrates at reduced pressures often results in reduced polishing removal rates and reduced substrate throughput. Barrier materials, such as tantalum (Ta) and tantalum nitride (TaN), are known to be chemically inert and difficult to polish at low pressure, resulting in large amounts of problematic barrier residues even after polishing by polishing compositions with high selectivity to barrier materials. Also other low adhesive cap materials, hard masks, and/or anti-reflective coating materials on top of the underlying dielectric materials are now exposed on the substrate surface. Overpolishing of the barrier residues and these protective materials by strong mechanical abrasion means metal loss, seam damage or device defect. On the other hand, low polishing pressure processes may be unable to sufficiently remove all of the desired barrier materials from a substrate surface. Such barrier materials or residues retained on the substrate surface can detrimentally affect device formation, such as creating short-circuits within or between devices, reducing device yields, reducing substrate throughput, and detrimentally affecting the polishing quality of the substrate surface. On the other hand, polishing at low pressure and high velocity (e.g., 0.5 psi/600 rpm) is commonly observed to be ineffective due to the hydroplaning effect where the removal is effectively zero.
Therefore, there exists a need for low-k compatible methods and related CMP compositions that use low shear force/down load force to prevent low-k dielectric damage and facilitate the effective removal of barrier materials and residues at a high removal rate.